library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity shiftLeft is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end shiftLeft;

architecture rtl of shiftLeft is
  begin
   C <= to_stdlogicvector(to_bitvector(A) sll (to_integer(unsigned(B(4 downto 0)))));
end architecture rtl;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity shiftRightLogical is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end shiftRightLogical;

architecture rtl of shiftRightLogical is
  begin
   C <= to_stdlogicvector(to_bitvector(A) srl (to_integer(unsigned(B(4 downto 0)))));
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity shiftRightArithmetic is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end shiftRightArithmetic;

architecture rtl of shiftRightArithmetic is
  begin
   C <= to_stdlogicvector(to_bitvector(A) sra (to_integer(unsigned(B(4 downto 0)))));
end architecture rtl;
---------------------------------------------------------------------------------